It is well known in processor-based systems to utilize so-called "interrupts" to change the program control flow of a processing device such as a microprocessor or a microcontroller to allow the processor to respond to real-time events. In typical applications, such events may include the receipt or transmittal of data by the system controlled by the processor.
When there are a number of different events to which the processor is required to respond, generally an equal number of different routines (referred to as "interrupt handling routines") are required, and it is also necessary for the processor to be able to determine which of the events has occurred so that the appropriate interrupt handling routine is initiated and carried out.
One known technique for determining which of a plurality of interrupt causing events (sometimes referred to as "interrupt sources") has occurred is to assign a separate terminal pin on the processor package to each of the possible interrupt sources. In that case, a signal received on a particular one of the interrupt pins is indicative of the occurrence of an interrupt originating with a respective one of the interrupt sources. However, the number of terminal pins provided with a processor is limited, and, in some processor-based systems, the number of possible interrupt sources may be large. As a result, techniques have been developed which allow a single interrupt pin to be shared by two or more interrupt sources. As is well known, in such a case the shared interrupt pin may or may not be the only pin used for receiving interrupts, and if there are other interrupt pins, those other pins may or may not be shared.
When a single interrupt pin is shared by two or more interrupt sources, the problem of determining from which source the interrupt has originated must again be dealt with. One of the known ways of solving this problem is to provide an interrupt status register with a plurality of storage locations, each of which acts as a flag for signaling that a respective interrupt source has originated the interrupt. When an interrupt signal is received on the shared pin, the processor performs a source determination routine in which it reads one or more of the flags in the interrupt status register and then goes on to perform an appropriate interrupt handling routine based on a determination of which flag or flags have been turned "on". Although this technique has been used with satisfactory results, nevertheless when a large number of interrupt sources share a common interrupt request pin, a relatively long time may be required to check flag-by-flag through the interrupt status register until the source of the interrupt is determined. For example, assuming that (a) sixteen different interrupt sources share a common interrupt request pin, (b) occurrences of the interrupts are randomly distributed among the sources, and (c) N clock cycles are required to check a flag in the interrupt status register, then on average (17/2).times.N clock cycles will be taken up with checking the interrupt status register flags prior to initiation of the needed interrupt handling routine. Again, solutions have been proposed, as in, for example, U.S. Pat. No. 4,908,745 to Ichiyasu et al. in which logic circuits are provided for dividing the interrupt sources into groups and indicating the group which includes the current interrupt source, so that only flags corresponding to interrupts in the indicated group need to be checked. However, the grouping arrangement once established according to the approach used by Ichiyasu et al. is fixed and lacks flexibility. Another known approach to reducing response time and interrupt handling overhead is to assign a higher priority to more frequently encountered interrupt sources.
With the increasing complexity of devices and the desire to further reduce the size of integrated circuit packages, there is a tendency to have more and more interrupt sources sharing a common interrupt request signal pin, and there is a need for more efficient and flexible approaches in determining the source of an interrupt.